Glossary - mîrifica home

entry	compact definition	alternate definition extended definition	area	notes
/*	* active low		logic	see also: ~
?AN	* area network
?AS	* address strobe		memory
?HCP	* hand circular polarization		radio communnications	LHCP, RHCP
?IF	* insertion force
?TC	* temperature coefficient		sensors
?W	*ware
*_B	* active low		Xilinx
$	cache			:-)
¥	cache			:-)
€	cache			:-)
1-Wire			bus	Maxim Integrated Products
ACET	average case ET	average case execution time
AEC	Automotive Electronics Council
AGU	address generation unit
AHB	Advanced High-performance Bus			ARM Limited
ALU	arithmetic logic unit
ARD	Address Range Definition		Xilinx IPIF
ARM	Acorn RISC Machine	Advanced RISC Machine
ASC	ASynChronous serial interface		Telit
ASCP	Application Specific Custom Product
ASIC	Application Specific Integrated Circuit
ASIP	Application Specific Instruction-set Processor
ASM	algorithmic state machine
ASSP	Application Specific Standard Product
AST	abstract syntax tree
ATA	AT attachment	advanced technology attachment
ATA/ATAPI-4			ATA	Ultra ATA/33
ATA/ATAPI-5			ATA	Ultra ATA/66
ATA/ATAPI-6			ATA	Ultra ATA/100
ATA/ATAPI-7			ATA	Ultra ATA/133
AUTO	auto-detect		networking
AVR	Alf Vegard Risc	Alf (Egil Bogen and) Vegard (Wollan's) Risc (processor)
B	binary
B2B	board-to-board
BB	base band
BBD	Black Box Definition		Xilinx
BBD	breadboard			prototyping board
BCCom	best-case commercial		RTOS
BCInd	best-case industrial		RTOS
BCMil	best-case military		RTOS
BD	buffer descriptor		Xiliinx Ethernet
BDM	background debug mode
BFM	Bus Functional Model		Xilinx
BGA	ball grid array
BIOS	basic input/output system		personal computer
BOB	Bipolar Offset Binary
BOM	bill of materials
BPI	Byte Peripheral Interface		Xilinx
BSP	board support package
BTB	board-to-board
BTC	Binary Two‘s Complement
C-cache	configurable cache
CAS	column AS	column address strobe	memory
CASE	computer-aided software engineering
CCL	CMOS configuration latch		Xilinx
CCLD	constant current line drive
CDFG	control data flow graph
CEP	circular error probable	circular error probability \| circle of equal probability	GPS
CFG	control flow graph
CISC	complex instruction set computer
CL	CAS Latency	Column Address Strobe Latency	memory
CLB	Configurable Logic Block		Xilinx
CLB	Configurable Logic Block
CLK	clock
CM	common mode
CMR	CM rejection	common mode rejection
CMRR	CMR ratio	common mode rejection ratio
CNC	computerized numerical control		automation
COB	Complementary Offset Binary
CoM	computer on module
CPI	cycles per instruction
CPLD	Complex PLD	Complex Programmable Logic Device
CPO	cycles per operation
CR	cognitive radio
CS	chip select
CSB	Complementary Straight Binary
CSBGA	chip-scale BGA
CSDF	cyclo-static data flow
CSP	Chip Scale Packaging		packaging
CTC	Complementary Two‘s Complement
D-cache	data cache
DAG	directed acyclic graph
DCF	Design rule for Camera File system		JEITA	JEITA
DCI	Digitally Controlled Impedance		Xilinx
DCIM	Digital Camera IMages		DCF CP-3461	DCF
DCM	digital clock manager		Xilinx
DCR	device control register		Power Architecture > CoreConnect
DCS	distributed control system		control
DFG	data flow graph
DFM	Design for manufacturability
DFT	data flow tree
diff	differential
DIL	dual in-line
DIMM	DIL memory module	dual in-line memory module
DIP	DIL package	dual in-line package	packaging
DLL	delay-locked loop		memory
DLP	digital light processor	digital light processing
DMMU	data MMU
DNP	do not populate
DNU	do not use
DQ	read data		memory
DQS	DQ strobe	read data strobe	memory
DRC	design rule check
DRX	discontinuous RX	discontinuous reception	radio communications
DSP	digital signal processing	digital signal processor
DTX	discontinuous TX	discontinuous transmission	radio communications
DUT	device under test
EABI	Embedded Application Binary Interface
ECC	Error Correcting Codes
EDA	electronic design automation
EDK	embedded development kit		Xilinx
ELF	Executable and Linking Format
EMAC	Ethernet Media Access Controller
EMS	electronic manufacturing services
EOL	end of life
EPIC	explicit parellel instruction computing
EPP	Enhanced Parallel Port
ERC	electrical rules check
ERD	entity-relationship diagram
ERP	effective radiated power		communications
ES	engineering sample		development
ESL	electronic system level
ET	execution time
EWB	etched wiring board
FA	full adder
FBGA	fine-pitch BGA
FCB	fabric coprocessor bus		Xilinx
FDC	floppy disk controller	floppy drive controller		see also: HDC
FESC	flow equivalent service center
FFC	flexible flat cable
FG	Flow Graph
FGND	frame ground
FLOPS	Floatingpoint OPS	Floatingpoint Operations Per Second
FMC	FPGA mezzanine card	VITA 57 ANSI/VITA 57.1-2008	form factor	www.vita.com/fmc.html
FP	frame pointer
FPC	flexible printed circuit (board)
FPGA	Field Programmable Gate Array
Fr	flame retardant			UL94-V0 [Underwriters Laboratories]
FR-4	FR type 4	flame retardant type 4
FSB	Fast Simplex Link (bus)		Xilinx
FSM	finite state machine
FSMD	finite state machines with datapath
FSR	full scale range		measurement systems
FU	functional unit
FW	firmware
FWFT	First Word Fall Through	First-Word Fall-Through
GA	gate array
GAL	generic array logic
GALS NoC	Globally Asynchronous Locally Synchronous NoC
GDSII	Gerber Data Stream Information Interchange
GMII	gigabit MII	Gigabit Media Independent Interface
GND	ground
GOA	general OA	general offset assignment
GP	general purpose
GPP	General Purpose Processors
GSC			RF connectors	muRata
GSR	global set reset
GSR	global Set/Reset		Xilinx
GSRN	GSR network	global set reset network
GTS	global 3-state	global three-state	Xilinx
GWE	global write enable		Xilinx
HA	half adder
HAN	home area network		networking
HART	highway addressable remote transducer		control or monitoring
HCMOS	high-speed CMOS
HCSL	high-speed current steering logic
HCT	HCMOS with TTL output	High-Speed CMOS with TTL output
HDC	hard disk controller	hard drive controller		see also: FDC
HDL	hardware description language
HDL	hardware description language
HDMI	high definition multimedia interface
HID	human interface device		USB
HSWAP	hot-swap		Xilinx
HSWAPEN	HSWAP enable	hot-swap enable	Xilinx
HW	hardware
I	input			see also:I/O
I-cache	instruction cache
I/O	input/output			see also: I, O
i.o.	instead of
I2C	IIC
IC	integrated circuit
IAP	in-application programming	in-application programming		see also: ICP, ICSP
ICE	in-circuit emulator
ICP	integrated circuit piezoelectric		PCB Group; PCB Piezotronics
ICP	in-circuit programmer	in-circuit programming		see also: ICSP, ISP
ICSP	in-circuit serial programmer	in-circuit serial programming		see also: ICP, ISP
ID	identifier	identification
IDC	insulation-displacement connector	insulation-displacement connection		see also: IPC
IEPE	integrated electronics piezo electric
IF	interface
IF	intermediate frequency
IGBT	insulated gate bipolar transistor		power electronics
IHV	independent hardware vendor			see also: IHS
IHS	independent software vendor			see also: IHV
IIC	Inter Integrated Circuit		bus
ILP	instruction level parallelism
ILP	integer linear programming
IMMU	instruction MMU
IOB	Input Output Bank	Input Output Block
IP	intellectual property (library element)
IPC	instructions per cycle
IPC	insulation piercing connector	insulation piercing connection		see also: IDC
IPIC	IP interconnect	intellectual property interconnect	Xilinx IPIF
IPIF	IP interface	intellectual property interface	Xilinx IPIF
IPMI	intelligent platform management interface		Intel
IPS	instruction per second
ISA	industry standard architecture		bus
ISA	instruction set architecture
ISC	Interrupt Source Controller		Xilinx IPIF
ISE	integrated software environment		Xilinx
ISP	instruction set processor
ISP	in-system programmer	in-system serial programmer		see also: ICP, ICSP
ISR	interrupt service routine
ISS	instruction set simulator
ISSP	Instant Silicon Solution Platform
ITE	if then else
JEITA	Japan Electronics and Information Technology Industries Association
JTAG	Joint Test Action Group			IEEE Std 1149.1-1990
KCPSM	k-coded programmable state machine	constant coded programmable state machine	Xilinx	PicoBlaze
LAN	local area network		networking
LAT	local address table
LBT	listen before talk		communications
LCA	Logic Cell Array
LE	logic element		Altera
LE	logic element
LHCP	left hand circular polarization		radio communications	RHCP
LIF	low insertion force
LL	LocaLink		Xilinx
LLC	leadless chip carrier		packaging
LLP	loop level parallelism
LMB	Local Memory Bus		Xilinx
LUT	look-up table
LVDS	low voltage differential signaling
LVPECL	low-voltage positive emitter-coupled logic
LVTTL	low voltage TTL	low voltage transistor-transistor logic
MAC	medium access control
MCB	memory controller block		Xilinx
MCI	Multimedia Card Interface		bus
MCM	multi-chip module		packaging
MCM	multi-chip module		packaging	see also: SiP
MCP	multi-chip package		packaging
MCU	micro controlling unit micro-controlling unit microcontrolling unit	micro-controller; microcontroller
MCU	Micro Controller Unit
MDCR	mode control register		Xilinx
MDI	medium dependent interface		networking
MDIX	MDI crossover		networking
MEMS	Microelectromechanical Systems
MFG	manufacturing
MHS	Microprocessor Hardware Specification		Xilinx XPS
MII	Media Independent Interface
MIMD	multiple instruction, multiple data (stream)			Flynn's taxonomy
MIPS	Microprocessor without Interlocked Pipeline Stages
MIPS	million IPS	million instruction per second
MIR	Module Identification Register		Xilinx
MISD	Multiple instruction, single data (stream)			Flynn's taxonomy
MMU	memory management unit
MOC	model of computation
Modbus	Modicon bus	Modicon communication bus	bus	Modicon, Gould-Modicon, Telemecanique, Schneider Electric
MOPB	master OPB		Power Architecture > CoreConnect
MOQ	minimum order quantity
MPSoC	Multi-Processor SoC	Multi-Processor System On Chip
MPU	micro processing unit; micro-processing unit; microprocessing unit	micro-processor; microprocessor
MPU	Micro Processor Unit
MSDS	material safety data sheet
MSS	Microprocessor Software Specification		Xilinx XPS
NAN	neighbouring area network		networking
NaN	not a number
NaT	not a thing
NC	not connected	no connect \| no connection
NCO	numerically-controlled oscillator
NEMA	National Electrical Manufacturers Association		body
NF	no function
NFC	near field communication
NMEA	National Marine Electronics Association		body
NoC	Network-on-Chip
NPI	Native Port Interface		Xilinx
NPU	network processing unit
NRE	non-recurring engineering		design and development
NTC	negative temperature coefficient		sensors	see also: PTC
NUAL	non-{uniform \| unit} {access \| assigend \| assumed} latency
O	output			see also: I/O
OA	offset assignment
OCM	On-Chip Memory (interface)		Power Architecture > CoreConnect
OCP	Open Core Protocol
ODM	original device manufacturer
ODT	on-die termination
OEM	original equipment manufacturer
OPB	On-chip Peripheral Bus		Power Architecture > CoreConnect
OPC	OLE for process control	object linking and embedding for process control	automation
OPS	operation per second
OS	operating system
OTP	one-time programmable		memory
PAL	programmable array logic
PAL	programmable array logic
PAN	personal area network
PAR	photosynthetically active radiation		optics
PC	personal computer
PCA	printed ciruit assembly
PCB	printed circuit board
PCBA	PCB assembly	printed circuit board assembly
PCI	peripheral component interconnect		bus
pCore	peripheral core		Xilinx
PCM	pulse-code modulation		communications
PCM	phase change memory		storage
PCS	Physical Coding Sublayer		Xiliinx Ethernet
PE	processing element
PFC	power factor correction
PGA	programmable gain amplifier
PIC	Peripheral Interface Controller	Programmable Interface Controller
PID	packet ID	packet identifier
PIM	Port Interface Module
PLA	programmable logic array
PLB	Processor Local Bus		Power Architecture > CoreConnect
PLC	programmable logic controller		automation
PLD	Programmable Logic Device
PLL	phase-locked loop
PMA	Physical Medium Attachment		Xiliinx Ethernet
Pmod	Peripheral Module		Digilent Inc.
PoCL	Power over Camera Link		National Instruments
POWER	Performance Optimized With Enhanced RISC		Power.org
PTC	positive temperature coefficient		sensors	see also: NTC
PTCRB	formerly: PCS Type Certification Review Board
PTH	Plated Through Hole
PWB	printed wiring board
QFE	quick-fix engineering	hotfix	development	Intel, Microsoft
RAS	row AS	row address strobe	memory
RC	release candidate
rc	runcom	run commands	posix
RF	radio frequency
RF	register file
RGMII	reduced GMII	Reduced Gigabit Media Independent Interface
RISC	rationalized instruction set computer	reduced instruction set computer
RHCP	right hand circular polarization		radio communications	LHCP
RJ	registered jack		networking
RT	real-time
RT	run-time
RTC	real-time clock
RTCM	Radio Technical Commission for Maritime Services		body
RTD	resistance temperature detector	resistive thermal device	sensor
RTL	Register Transfer Level
RTM	release to manufacturing	release to marketing	development
RTOS	real-time OS	real-time operating system
RX	reception	receiver
SA	selective availability		GPS
SCLK	serial CLK	serial clock
SDI	serial data in			MISO: Master in Slave out
SDK	embedded development kit		Xilinx
SDL	Specification and Description Language
SDO	serial data out			MOSI: Master out Slave in
SDR	software defined radio
SE	single ended
SFP	small form-factor pluggable		transceiver
SGMII	serial GMMI	Serial Gigabit Media Independent Interface
SIE	Serial Interface Engine
SIMD	Single instruction, multiple data streams			Flynn's taxonomy
SiP	system in (a) package		packaging	see also: MCM
SISD	Single instruction, single data stream			Flynn's taxonomy
SKU	Stock-keeping unit		logistics, software
SLI	system level integration
SMB	System Management Bus		bus
SMBus	System Management Bus
SMD	surface-mount device
SMP	symmetric multiprocessing
SMPS	switched-mode power supply	switching-mode power supply
SMT	surface-mount technology
SO-DIMM	small outline DIMM
SOA	simple OA	simple offset assignment
SoC	system on (a) chip
SODIMM	small outline DIMM
SOPB	slave OPB		Power Architecture > CoreConnect
SP	stack pointer
SPDT	single pole double throw
SPI	serial peripheral interface
SPM	scratchpad memory
SPS	Speicherprogrammierbare Steuerung	stored-program control	automation	German language. See also: PLC
SRR	Software Reset Register		Xilinx
SS	slave select
SSI	serial synchronous interface
SSO	simultaneous switching output
SSP	serial synchronous port		communications
SSTL	Stub Series Terminated Logic		memory
STA	static timing analysis		synchronous digital design
STAPL	Standard Test and Programming Language		ISP, CPLD
STE	Slave Transmit Enable
STM	STMicroelectronics	SGS Thomson Microelectronics
SW	software
tact	tactile (switch)
TAP	test access port		JTAG
TBD	to be determined
TCK	Test Clock		JTAG
TCM	tightly coupled memory
TCXO	temperature controlled crystal oscillator			X = crystal (!)
TDI	Test Data Input		JTAG
TDO	Test Data Output		JTAG
TH	Through Hole
THT	through-hole technology
TIG	Timing IGnore		Xilinx
TLB	translation lookaside buffer
TLM	transaction level modeling
TMS	Test Mode Select Input		JTAG
TP	test point
TSR	total solar radiation		optics
TT	transaction translator		USB
TX	transmission	transmitter
U-DIMM	unregistered DIMM
U.FL			RF connectors	Hirose: See also IPEX.
UART	Universal Asynchronous Receiver Transmitter
UCF	user constraints file		Xilinx
UDIMM	unregistered DIMM
UL	Underwriters Laboratories
ULP	ultra low power
ULPI	UTMI+ Low Pin Interface
uP	micro processor
UR	UL Recognition	Underwriters Laboratories Recognition
USART	Universal Synchronous/Asynchronous Receiver Transmitter
USB	Unipolar Straight Binary
USB	universal serial bus
USBTMC	USB Test & Measurement Class
USIC	User Programmable IC	user programmable integrated circuit
UTMI	USB 2.0 Transceiver Macrocell Interace		USB
UTMI+	UTMI extension		USB	supports USB host and On-The-Go
VITA 57	ANSI/VITA 57.1-2008	FMC	form factor	www.vita.com/fmc.html
VHDL	VHSIC HDL	VHSIC hardware description language
VHDL-AMS	VHDL analog mixed-signal
VHSIC	Very-High-Speed Integrated Circuit
VLIW	very long instruction word
VSI	Virtual Socket Interface
VSIA	VSI Alliance			Mentor Graphics, Cadence Design Systems, Magma Design Automation, ARM Holdings, Synopsys; dissolved in 2008
w/	with
w/o	without
W?AN	wireless * area network
WAN	wide area network		networking
WCCom	worst-case commercial		RTOS
WCET	worst-case ET	worst-case execution time
WCInd	worst-case industrial		RTOS
WCMil	worst-case military		RTOS
WLCSP	Wafer Level CSP	Wafer Level Chip Scale Packaging	packaging
WSN	wireless sensor network
X	crystal			!
X	don't care state
XCF	XST Constraint File		Xilinx
XCL	Xilinx Cache Link		Xilinx
XCVR	transceiver
XIP	execute in place
XMFR	transformer
XPS	Xilinx platform studio		Xilinx
XST	Xilinx Synthesis Technology		Xilinx
XUP	Xilinx University Program		Xilinx
Z	high impedence state
ZIF	zero insertion force
~*	* active low		logic	see also: /
µP	micro processor

static timing analysis

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