Prezzo IVA esclusa (inclusa) più spese di spedizione.
Supplier lead time: 10 giorni lavorativi
- Codice Mirifica: 100271
- Codice MEPA: MFMP-100271 (+ MFMP-SPESE_FISSE, opz. "codici del catalogo")
- Nome produttore: Zeroplus Technology
- Codice produttore: LAP-C16064
- A magazzino: 0
- Supplier lead time: 10 giorni lavorativi
The LAP-C is Zeroplus bestselling logic analyzer series. Launched in 2008, it won the ELEXCON Excellent Product Award in 2008 and the Taiwan Excellence Award in 2009. It also became an immediate commercial success with more than 25,000 units sold to date. With functions, specifications and analysis tools that are remarkable for the price class, intuitive setup and software and a huge library of protocol decoders, many years after release the LAP-C still offers unparalleled value for money.
The Buttons on the Logic Analyzer Hardware Own the Function of Sampling:
There is a START button on the hardware of the Zeroplus Logic Analyzer, and pressing this button can make the Logic Analyzer sample signals when the software of Logic Analyzer is activated. Users can quickly capture data from the testing board by using the START button.
Zeroplus Technology issues the patent technology of Waveform Compression which can capture more waveform data without adding the size of the RAM.
For example: The RAM Size is set as 1M, and the Sampling Frequency is set as 50MHz. When the Compression function is not activated, Zeroplus Logic Analyzer can only capture waveform data within 20.972ms; when the Compression function is activated, with the same RAM Size (1M) and Sampling Frequency (50MHz), the Logic Analyzer can prolong the waveform data to 3.999s. That is to say, the function of Waveform Compression can improve the amount of the captive data largely.
Signal Filter Delay
Zeroplus Technology issues the patent technology of Signal Filter Delay. The function of the Signal Filter Delay can capture the signals conditionally. For example, the Filter Condition of channel A1 is set as High Level; the differences can be seen obviously by the horizontal windows, and the Filter Delay Setup can make the conditions of the Signal Filter more flexible; users can set the time of the Filter Delay as their requirements.
For example: Clients found Bugs in a group of DUT. The content of the Bug is that a read error may be presented while the program tries to read the data. At that moment, users can use the function of the Signal Filter Delay to capture signal conditionally and analyze the Bug further（the Status of the Read is 0X5A, the Command Period of the Read is 10us）. According to the function of the Signal Filter Delay, Zeroplus Logic Analyzer can only capture the 10us Command Period to analyze the Bug when the Data of 0X5A is presented.
Zeroplus Logic Analyzer adds the patent technology of Trigger Page, in other words, the Trigger Page is to page the continuous and long signal data.
Take the set RAM Size as one page, and the position of the trigger point is the first page. After analyzing the data of the first page, users can set the Trigger Page as “2” and restart the Logic Analyzer when the data of the testing board are the same for each time and the setting of the trigger condition is not to be changed; when the Logic Analyzer stops capturing the data and completes the display, the content of the Waveform Display Area is the data of the second page which follows the data of the first page.
For example: The RAM Size is set as 32K; the Sampling Frequency is set as 200MHz; the Trigger Page is “1”. The end point of the captured signal is 147.465us and the former half part of the data is 0X47. When starting to capture with the same RAM Size and Sampling Frequency and setting the Trigger Page as “2”, the start point of the captured data is 147.465us which is the end point of the first page, and users can see the latter part of the data, 0X47.
Zeroplus Logic Analyzer adds the technology of Trigger Count. The Trigger Count function is suitable for this kind of tested signals which have more than one trigger signal according with the Trigger Condition. Users can decide the trigger position where the trigger signal accords with the Trigger Condition. When users want to trigger at the first time when the trigger signal accords with the Trigger Condition, the setting of Trigger Count should be “1” (it is the default); when users want to trigger at the third time when the trigger signal accords with the Trigger Condition, the setting of the Trigger Count should be “3”; the others can follow the former method.
The Max. Trigger Count can be set as “65535”.
Zeroplus Logic Analyzer adds the function of Chain-Data-Find. The original function of Find Data Value can find only one data , and the function of Chain-Data-Find enhances the Find function; for instance, the signal owns the chain data which are 0X01, 0X02, 0X03…0X25, 0X26, 0X27…0X40, then it can set the 0X25, 0X26 and 0X27 as the target of Find; it improves the efficiency of analyzing the signal.
The Analysis Example of Protocol Analyzer - The Decoding of Protocol Analyzer IIC
The Protocol Analyzer IIC Analysis Module of Zeroplus Technology can help users to analyze the Protocol Analyzer IIC. The packet segments of START, ADDRESS, DATA, ACK, NACK, STOP in signals can be directly displayed on the screen according to the Analysis Module. The Protocol Analyzer IIC Analysis Module of Zeroplus Technology provides the function of setting Address and Data Bit as users requirements. It won’t be limited by the special specifications when analyzing the IIC signal; users can set the range from 1bit to 28bit as their requirements.
- Internal Clock (Timing Mode) 100 Hz ~ 100 MHz
- External Clock (State Mode) 100 MHz
- Bandwidth：75 MHz
- Working Range： -6V~+6V
- Accuracy： ±0.1V
- Memory：1 Mbits
- Depth(Per Channel)：64 Kbits (Max 16 Mbits for compression)
- Condition： Pattern/Edge
- Trigger Channel ： 16 CH
- Post Trigger： YES
- Trigger Level： 1 Level
- Trigger Count： 1~65535
- Data Compression : Max 64 K bits x 256
- Time Base Range : 5ps~10Ms
- Language : Chinese (Traditional/Simplified) English
- Maximum Trigger Page : 8192 Pages
- Waveforrm Data Display
- Filter&Filter Delay
- Trigger Delay
- Unlimited lncreasing Bar
- Automatic Attaching Bar
- Automatic Software Upgrade
- Data Statistic
- Filter Bar
- Protocol Analysis
- Protocol Packet List
- File Export
- Data Contrast : Not support
- Latch Function: Not support
- Protocol Analyzer Trigger: parallel
- Pulse Width Trigger Module : option
- Power ：USB (DC 5V, 500mA)
- Operating System： Windows 2000 / XP(32bits) / Vista / Win 7
- Phase Errors： < 1.5ns
- Maximum Input Voltage： ±30V
- Safety Certification： FCC / CE / WEEE / RoHS / REACH
Extending Channel Capture
- Not supported
- Not supported
|Working Voltage||DC 4.5V||DC 5V||DC 5.5V|
|Current at Rest||–||–||200mA|
|Current at Work||–||–||400mA|
|Power at Rest||–||–||1W|
|Power at Work||–||–||2W|
|Error in Phase Off||- 1.5ns||–||+ 1.5ns|
|Vinput of Testing Channels||- DC30V||–||+ DC30V|
|Vreference||- DC6V||–||+ DC6V|
|Working Temperature||5 ℃||70 ℃||–|
|Storage Temperature||-40 ℃||–||80 ℃|
How it Works
Example: Decoding of Protocol Analyzer IIC
Plug the testing cable into the signal connectors of the Logic Analyzer, and connect the other ends of the testing cable to the testing board; users can use the probe in the package to connect with the testing board according to the different conditions of the testing board.
Set the conditions of the Logic Analyzer according to the Chapter 3 of the Installation Guide, and then activate the Logic Analyzer’s software and send out the signal of the testing board to start capturing; the captured signal appears as below.
PS: The sampling frequency of Logic Analyzer should be more than 4 times higher than that of the testing board to make sure the signal is accurate.
Group the unanalyzed channels into Bus: press the CTRL key on the keyboard continuously, and use the mouse to click the unanalyzed channels to highlight them; when the selection is completed, click the Right Key on the mouse to select the option of “Group into Bus”; there will be a Bus added in the Bus/Signal column.
PS: When starting the Bus Analysis, set the number of channels according to the tested Protocol Analyzer, for instance, the Protocol Analyzer IIC needs two channels to start the analysis, and the Protocol Analyzer UART needs one channel to start the analysis.
Select Bus1, and press the Right Key on the mouse; click Bus Property to open the Bus Property dialog box, and then select the desired Protocol Analyzer. There is a corresponding Parameters Configuration setting for each Protocol Analyzer; users can set the relative contents of the Protocol Analyzer in the Parameters Configuration dialog box according to the tested Protocol Analyzer. Below is an example.
PS: According to the Protocol Analyzer IIC Analysis Module of Zeroplus Logic Analyzer, users can set the Number of Bit for Address and Data as their requirements in the Custom Setting dialog box and the setting range is 1 ~ 28 Bits.
When the setting is completed, the packet data of the Protocol Analyzer IIC will be displayed on the screen.
PS: The software of Zeroplus Logic Analyzer owns other powerful functions to help users to start the Bus analysis, such as Packet List, Find Data Value, Find Pulse Width, and so on.
- 16 channel testing cable packagpe (25cm)
- USB cable
- Probe(testing hooks): 20 pieces
- Install Disk
- Installation Guide
- Carry Bag