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Alinx Electronic Limited
Alinx 100G Ethernet UDP/IP Stack FPGA IP Core for Network Acceleration
Developed based on AMD/Xilinx 100G Ethernet MAC IP, MTU data transmission up to 9000 bytes, AXI4 stream interface, supporting UltraScale / Ultrade+ / Zynq UltraScale+ Series FPGA devices, high bandwidth and low latency, fast data transmission and real-time processing, accurate and efficient data transmission of UDP protocol stack.
Item number VAR-827003733
Manufacturer Product Number: 100G Ethernet UDP/IP
Taric/custom code:
Imported produkt is shipped from Riedlingen, Germany
Product Description
Developed based on AMD/Xilinx 100G Ethernet MAC IP, MTU supports up to 9000 bytes of data transmission, standard AXI4 Stream interface, supports AMD/Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Artix UltraScale+ Series FPGA devices. The 100G Ethernet with high bandwidth and low latency ensures fast data transmission and real-time processing, while the UDP protocol stack further improves the efficiency and accuracy of data transmission.
We provide you with a fast, reliable, low-cost, and high-performance solution that significantly shortens the time to market and is suitable for high bandwidth, low latency, and high-speed data transmission scenarios.
Applications
? Data Center
? Cloud Computing Storage
? AI
? Machine Learning
? Telecommunications
? Industrial Automation
? Internet of Things
? Medical
? Gene Sequencing
? 4K/8K HD Video Transmission
? Scientific Research Experiment
? Financial Transactions
? Test Measurement
Key Features
? Implement an ARP/IPV4/ICMP/UDP protocol stack that complies with the IEEE802.3 standard based on the OSI layered model.
? Supports ARP for obtaining or sending MAC addresses.
? Supports ICMP for responding to Ping commands.
? ARP responds to all incoming requests, only stores 10 ARP tables.
? No UDP packets are sent if the ARP table is not established.
? 100Gbps Ethernet connection, supporting UDP/IP checksum processing, calculating CRC by the MAC IP.
? Developed based on AMD/Xilinx 100G MAC IP, supporting MTU up to 9000 Bytes and a minimum 64 Bytes data transmission size.
? AXI4 Stream interface for users, with the protocol stack using a clock of 322.266 MHz generated by the MAC IP, and a 100 Gbps data bus width of 512 bits.
